The size of the LDE depends on the order of the compensator and the method used to transform the continuous frequency function to a discrete frequency function (forward/backward Euler, bi-linear Transform, etc.). Simply put, the LDE is a mathematical expression that uses linear combinations of the control errors and previous control outputs to produce the current control output. See Figure 2 for an example of a 3P3Z linear difference equation.
It can be seen that for the 3P3Z compensator there are seven multiplications and additions that need to occur in order to determine the desired control output. This type of arithmetic is well suited for the architecture of the dsPIC33 devices. These instructions can be processed in seven single cycle instructions using the multiply and accumulate (MAC) instruction. However there is going to be additional software overhead that includes: push/pop working registers, loading data in/out of working registers, resetting arrays, and clamping/scaling the control output. This overhead can potentially impact the control loop execution rate which leads to reduced phase margins.
As shown earlier, with the increased MIPS the execution time for the control loop has dropped quite a bit. However, this can be improved even further on the new dsPIC33EP ‘GS’ devices with the addition of alternate working registers. These devices incorporate two additional banks of 15 working registers that can be made persistent. This means data such as clamp limits, scaling factors, pointers to coefficients, etc. can be preloaded into appropriate alternate working registers at the device initialization stage. These register banks can then be associated to a given interrupt priority level which only the control loop software would have access to. This will then eliminate the need to push/pop working registers onto the stack and will reduce the overhead of getting data into work registers when executing the compensator algorithm.
Figure 3 is an example of how to successfully utilize an alternate working register set using Microchip’s hardware accelerated compensator functions. It is important to remember that certain registers are required for particular instructions which impose limitations to where data can be placed.
Let’s consider the impact of the alternate working registers on MIPS consumption for high frequency control loops. A compensator algorithm that may have been called every other switching cycle on the dsPIC33FJ devices may now be called every switching cycle and would still utilize the same percentage of MIPS. The phase erosion due to the sampling process was given in Figure 1. The amount of phase degradation depends on the crossover frequency and sampling frequency. Therefore if the sampling rate is doubled, the phase degradation is reduced by half. This means that the phase erosion went from a 29% reduction due to device operating speeds to a 50% reduction when including the use of the alternate working registers.
To illustrate the reduction in phase erosion due to sampling frequency, consider a system with a 175kHz sampling frequency and 10kHz bandwidth, the phase erosion is calculated as roughly 10 degrees. The same system with 350kHz sampling frequency would only have 5 degrees of phase erosion. This additional phase margin can be achieved with the dsPIC33EP device while utilizing the same percentage of MIPS as compared to the dsPIC33FJ devices.
It has been shown that higher sampling frequencies can be obtained with the use of alternate working registers and faster operating speeds of the dsPIC33EP devices leading to reduced phase erosion. Next, let’s discuss other device specific peripherals and techniques that can improve phase margin leading to improved loop gain performance.
The dsPIC33EP ‘GS’ family of devices include a new 12-bit ADC that incorporates multiple Successive Approximation Register (SAR) cores. The device is capable of sampling multiple analog inputs simultaneously and having dedicated 12-bit results available in less than 300ns. The dedicated SAR cores are continuously tracking the input signal which means there is zero sampling time required. When the ADC sees a trigger event it will automatically start the conversion process. Remembering that the sampling/conversion time is seen as a delay in the control loop, it will minimize the overall sampling/conversion latency will help with phase margin erosion.
