Introduction
High speed differential amplifiers help to drive high performance analog-to-digital converters (ADCs) by providing balanced drive to the differential input stage, setting the common mode level, absorbing the sampling-energy, and taking gain to reduce the output swing requirement of preceding circuitry. In applications involving multiple ADCs, a compact, tightly matched dual differential amplifier such as the LTC6420-20 can further simplify the design by reducing the uncertainty of channel-to-channel variations.
The LTC6420-20 features two 1.8GHz differential amplifiers, each capable of driving 12-, 14- and 16-bit pipeline ADCs at low noise and low distortion levels, even for input frequencies as high as 300MHz. The internal op amps are manufactured on a Silicon Germanium (SiGe) process and feature an ultra-low 1nV/√Hz noise density. Even after factoring in the internal feedback resistors, the total input noise density equals only 2.2nV/√Hz. The channel-to-channel gain matching is production tested and guaranteed to be better than ±0.25dB. Moreover, the monolithic design ensures that both phase and group delay remain tightly matched over the entire bandwidth of the amplifiers.
The dual amplifier is available in a 3mm × 4mm QFN package, which saves space compared to two single amplifiers. For further space-savings, all gain and feedback resistors are included on-chip, setting a fixed voltage gain of 20dB. The LTC6420-20 consumes 80mA per channel from a supply as low as 2.85V. A 40mA version, the LTC6421-20, is available to save power at the expense of usable input bandwidth.
Wideband Interface between an I/Q Demodulator and a Dual ADC
When an IF or RF signal is applied to a demodulator such as the LT5575, the signal’s information is separated out into two baseband signals: “in-phase” (I) and “quadrature” (Q). Both baseband signals need to be digitized simultaneously, and it is critical that the relationship of gain and phase between the two is maintained. Furthermore, if you want to maximize the dynamic range by driving the dual ADC close to full scale, without driving the demodulator so hard that it causes excessive distortion, you need to insert some gain between the demodulator output and the ADC input. In Figure 1, the LTC6421-20 provides this gain, while the tight matching between its two channels contributes a negligible amount of gain or phase error. The bandwidth and linearity of the LTC6421-20 ensures that 14-bit linearity (distortion less than –84dBc) is maintained to 50MHz and beyond, an important design criteria in digital-predistortion (DPD) circuits or wideband receivers.
Figure 1. The voltage gain of the LTC6421-20 reduces the output swing requirements of the LT5575 demodulator. This improves overall system linearity.
Paralleling Two Drivers to Lower the Noise Floor
In applications with only one ADC, you can hook-up the two channels of the dual amplifier in parallel, as shown in Figure 2. The main benefit of doing so is a reduction in noise, because the random noise contributions of each channel get averaged out. For example, input noise density (with inputs shorted) drops from 2.2nV/√Hz to 1.5nV/√Hz, a 3dB improvement in SNR if the driver were the dominant noise source.
Figure 2. Connecting the two channels of the LTC6420-20 in parallel reduces the noise floor.
Conclusion
The LTC6420 features two high speed differential amplifiers in a small 3mm × 4mm QFN package, with guaranteed tight matching specs between the two channels. It is ideal for driving high frequency signals into dual ADCs, especially when board space is limited or when the magnitude and phase relationship between the signals must be preserved.
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